Certain methods of receiving high speed data signals involve sampling an incoming data stream and determining the logic state of each symbol period of the incoming signal. Based on the determined logic state, the data stream is re-generated locally for further processing. The process of determining and re-generating the sampled logic state is known in the art as resolving the logic state. The process of sampling and resolving the data takes an increasingly significant amount of time as the data transmission rates increase. At rates above 10 Gb/s, the sampling and re-generating time becomes a bottleneck, and a solution for improving the data resolving time is needed.
Various solutions have been proposed to address the issues associated with high speed data sampling as described, for example, in U.S. Pat. Nos. 6,252,441, 6,538,486, 6,580,763, 6,850,580 and U.S. Publication Application Nos. 2002/0184564A1 and 2003/0118138A1.
One problem associated with receiving high data rates is the difficulty with accurately resolving the received data. Lower signal voltages are preferred for high-speed data transmission to reduce the time needed to transition the signaling from one logic state to another. However, signal receiving circuits can exhibit a substantial input offset voltage that directly limits the minimum input signal level that can be successfully resolved by the sampling circuit. A solution is therefore needed for improving the receiving circuitry's ability to resolve signals having a low amplitude that approaches the input offset voltage of the receiver circuitry.